1. Field of the Invention
This invention relates to data processing systems. More particularly, this invention relates to data processing systems using asynchronous first-in-first-out (FIFO) buffer circuit for passing data words between a first circuit block and a second circuit block operating with different clock signals that have no fixed phase relationship.
2. Description of the Prior Art
It is known to provide asynchronous FIFOs within a clocked system to communicate between two different clocking domains. In this way, it is possible for the circuits within the two domains to interact and yet the needs for clock synchronisation can be eased.
It is also known for different parts of a data processing system to exchange data words in what is termed a burst mode of operation. An example of a burst mode of operation is where a given transfer starts with the destination address followed by a sequence of words that are to be written in sequentially ascending address locations starting from the address specified. (The address and data may be passed via a common FIFO or may each have their own FIFO.) This burst mode is more efficient in terms of bandwidth and power consumption than separately transmitting the address of each word of data to be written when these are following an entirely predictable sequentially increasing address order.
It is also desirable to use a burst mode of operation when communicating using an asynchronous FIFO so as to reduce any synchronisation penalty when reading words from the FIFO. In order for a second circuit block to determine if the FIFO contains a data word it must first synchronise to the second block clock domain the signal from the last stage of the FIFO that indicates whether or not it contains a data word. If a burst mode is not available, then this penalty must be incurred on every read. If a burst mode of operation is provided, then the first word in a burst will incur this penalty, but subsequent words in the burst can be read without any clock synchronisation penalty as long as the last word in a burst can be identified. One way for this mechanism to work is that subsequent words should be available at the bottom of the FIFO once the preceding word has been read. This may be achieved by using a reading clock frequency that is less than or equal to the writing clock frequency and for the words in a burst to be inserted into the FIFO on consecutive clock cycles.
As the operational speeds of data processing systems have increased, it has become desirable to write data words into a FIFO buffer circuit disposed between clock domains at the highest possible rate. When operating at such high rates, a data word within a burst mode of transfer may need to be written into the FIFO buffer circuit before the originating circuit has determined whether or not that data word will be the last word of that particular burst. This imposes a potential constraint on the increase in speed of operation of the system since the circuit that will read the words out from the FIFO buffer circuit needs to be able to identify the last word in a burst.
It is an object of the present invention to provide data processing systems using an asynchronous FIFO buffer circuit between different clocked domains that is able to operate at high speeds by addressing the above mentioned problems.